jleightcap Jack Leightcap
github.com/jleightcap · maintains 23 packages (23 directly), sole maintainer of 6, member of 0 teams
23 packages
| Package ▲ | Version | Maintainers | # | Teams | Deps | Used by | Used by (transitive) | Status |
|---|---|---|---|---|---|---|---|---|
VCD/Waveform viewer for Unix and Win32 |
3.3.128 |
3 | 12 | 2 | 25 | maintained | ||
Visual editor for open FPGA boards |
1.0.0.PRw-20260821-unstable-2026-08-20 |
8 | 10 | 0 | 0 | maintained | ||
Librecast multicast agent |
0.1.0 |
2 | 7 | 0 | 0 | maintained | ||
Librecast RaptorQ library |
0.4.1 |
5 | 2 | 3 | 3 | maintained | ||
Librecast File and Syncing Tool |
0.3.2 |
5 | 5 | 0 | 0 | maintained | ||
Microlibrary for X25519/Ed25519 cryptography |
20260614 |
7 | 5 | 0 | 0 | maintained | ||
Microlibrary for counting CPU cycles |
20260105 → 20260901 |
3 | 3 | 1 | 1 | maintained outdated | ||
Simple API for applications generating fresh randomness |
20240318 |
3 | 4 | 1 | 1 | maintained | ||
IPv6 multicast library |
0.11.2 |
9 | 4 | 2 | 2 | maintained | ||
Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python |
2.0.1 → 2.1.0 |
2 | 21 | 0 | 0 | maintained outdated | ||
Python module for calculating and verifying predefined & custom CRC's |
7.1.0 → 8.0.0 |
1 | 17 | 3 | 3 | single outdated | ||
Tool to help modeling engineers extract model parameters, run circuit and TCAD simulations and automate infrastructure |
2.1.0 |
6 | 33 | 0 | 0 | maintained | ||
Finds the libpython associated with your environment, wherever it may be hiding |
0.5.1 |
1 | 18 | 1 | 1 | single | ||
Module for binding variables and refreshing multi-line output in terminal |
0.6.0 |
2 | 18 | 1 | 1 | maintained | ||
Verilog-A tool useful for compact model parameter extraction |
24.0.0mob-unstable-2026-08-01 |
2 | 23 | 1 | 1 | maintained | ||
Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python |
2.0.1 → 2.1.0 |
2 | 21 | 0 | 0 | maintained outdated | ||
Python module for calculating and verifying predefined & custom CRC's |
7.1.0 → 8.0.0 |
1 | 17 | 4 | 6 | single outdated | ||
Tool to help modeling engineers extract model parameters, run circuit and TCAD simulations and automate infrastructure |
2.1.0 |
6 | 33 | 0 | 0 | maintained | ||
Finds the libpython associated with your environment, wherever it may be hiding |
0.5.1 |
1 | 18 | 1 | 1 | single | ||
Module for binding variables and refreshing multi-line output in terminal |
0.6.0 |
2 | 18 | 1 | 1 | maintained | ||
Verilog-A tool useful for compact model parameter extraction |
24.0.0mob-unstable-2026-08-01 |
2 | 23 | 1 | 1 | maintained | ||
Assembler and emulator for the Uxn stack machine |
1.0-unstable-2025-11-20 → 20250907 |
1 | 3 | 0 | 0 | single outdated | ||
X11 and standalone text-mode emulators for the Uxn virtual machine |
1.0-unstable-2025-09-27 |
1 | 3 | 0 | 0 | single |