gonsolo Andreas Wendleder
github.com/gonsolo · maintains 16 packages (16 directly), sole maintainer of 10, member of 0 teams
16 packages
| Package ▼ | Version | Maintainers | # | Teams | Deps | Used by | Used by (transitive) | Status |
|---|---|---|---|---|---|---|---|---|
Open RTL synthesis framework and tools |
0.69 |
5 | 15 | 11 | 22 | maintained | ||
SystemVerilog compiler and language services |
10.0 |
3 | 9 | 0 | 0 | maintained | ||
YAML 1.2 Support for PyYAML |
0.0.4 |
1 | 18 | 1 | 1 | single | ||
Formal RISC-V architecture model in Python |
0.6.6 |
1 | 19 | 0 | 0 | single | ||
Python library for parsing Yosys output |
0-unstable-2025-08-30 |
1 | 17 | 1 | 1 | single | ||
C++/Python library for creation and manipulation of GDSII and OASIS files |
1.0.0 → 1.0.1 |
5 | 24 | 0 | 0 | maintained outdated | ||
Open RTL synthesis framework and tools |
0.69 |
5 | 15 | 3 | 7 | maintained | ||
YAML 1.2 Support for PyYAML |
0.0.4 |
1 | 18 | 0 | 0 | single | ||
Formal RISC-V architecture model in Python |
0.6.6 |
1 | 19 | 0 | 0 | single | ||
Python library for parsing Yosys output |
0-unstable-2025-08-30 |
1 | 17 | 0 | 0 | single | ||
C++/Python library for creation and manipulation of GDSII and OASIS files |
1.0.0 → 1.0.1 |
5 | 24 | 0 | 0 | maintained outdated | ||
Tool for managing Process Design Kits (PDKs) for ASIC and FPGA flows |
3.0.0 |
1 | 21 | 1 | 1 | single | ||
LVS tool for VLSI circuit netlists |
1.5.323 |
1 | 5 | 1 | 1 | single | ||
ASIC implementation flow infrastructure |
3.0.14 → 3.0.15 |
1 | 42 | 0 | 0 | single outdated | ||
C++/Python library for creation and manipulation of GDSII and OASIS files |
1.0.0 |
5 | 6 | 0 | 0 | maintained | ||
High performance layout viewer and editor with support for GDS and OASIS |
0.30.12 |
1 | 18 | 1 | 1 | single |