master · x86_64-linux · cf9005753f89 · generated 2026-10-08T00:45:57Z
102,173packages 38,704unmaintained (37.9%) 41,810single maintainer (40.9%) 9,522team only (9.3%) 8,396broken 12,474outdated (12.2%) 4,912maintainers 85teams 206setup hooks (hidden)

gonsolo Andreas Wendleder

github.com/gonsolo · maintains 16 packages (16 directly), sole maintainer of 10, member of 0 teams

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16 packages

Package ▲ Version Maintainers # Teams Deps Used by Used by (transitive) Status
High performance layout viewer and editor with support for GDS and OASIS
0.30.12
1
18 1 1 single
C++/Python library for creation and manipulation of GDSII and OASIS files
1.0.0
5 6 0 0 maintained
ASIC implementation flow infrastructure
3.0.14 → 3.0.15
1
42 0 0 single outdated
LVS tool for VLSI circuit netlists
1.5.323
1
5 1 1 single
Tool for managing Process Design Kits (PDKs) for ASIC and FPGA flows
3.0.0
1
21 1 1 single
C++/Python library for creation and manipulation of GDSII and OASIS files
1.0.0 → 1.0.1
5 24 0 0 maintained outdated
Python library for parsing Yosys output
0-unstable-2025-08-30
1
17 0 0 single
Formal RISC-V architecture model in Python
0.6.6
1
19 0 0 single
YAML 1.2 Support for PyYAML
0.0.4
1
18 0 0 single
Open RTL synthesis framework and tools
0.69
5
15 3 7 maintained
C++/Python library for creation and manipulation of GDSII and OASIS files
1.0.0 → 1.0.1
5 24 0 0 maintained outdated
Python library for parsing Yosys output
0-unstable-2025-08-30
1
17 1 1 single
Formal RISC-V architecture model in Python
0.6.6
1
19 0 0 single
YAML 1.2 Support for PyYAML
0.0.4
1
18 1 1 single
SystemVerilog compiler and language services
10.0
3
9 0 0 maintained
Open RTL synthesis framework and tools
0.69
5
15 11 22 maintained